1. Field of the Invention
The present invention relates to a voltage level shifter, and more particularly to a dual supply voltage input/out buffer capable of interfacing between two circuit systems having different voltage swings.
2. Description of the Prior Art
Historically, the primary mode of reducing power consumption in electronic circuits has been to insistently scale down the power supply voltage. Recently, a move to 1.8 V power supply has been popularized among low-power and high-speed circuit designers. Problems may arise where both low and high voltage integrated circuits are connected together. An integrated circuit operating on a lower voltage must then provide an output at the higher voltage.
A typical solution to this problem is to add an intermediate voltage level shifter between an internal circuitry having a low voltage swing and an external circuitry having a high voltage swing. A special concern has been focused on a 3.3 V driver for 1.8 V process.
Please refer to FIG. 1. FIG. 1 is a circuit diagram schematically illustrating a voltage level shifter 100 according to the prior art. The voltage level shifter 100 of the prior art comprises a first transistor 111, a second transistor 112, a third transistor 121, a fourth transistor 122, and an inverter 131. In addition, there is a reference voltage generator, not shown in the figure, for providing a high supply voltage VCCH and a low supply voltage VCCL.
The voltage supply of the inverter 131 is the low supply voltage VCCL. The external output signal VOUT 114 is taken out from the first contact point 113.
The inverter 131 functions to invert the external input signal VIN 133 to generate an internal input signal VX 134 at the third contact point 132. That is, the internal input signal VX 134 is at a low voltage while the external input signal VIN 133 is at a ground voltage and the internal input signal VX 134 is at a ground voltage while the external input signal VIN 133 is at a low voltage.
The second transistor 112 in conjunction with the first transistor 111 acts to perform an inverting process having different voltage swings between inputting and outputting. That is, the external output signal VOUT 114 is at a high voltage while the internal input signal VX 134 is at a ground voltage and the external output signal VOUT 114 is at a ground voltage while the internal input signal VX 134 is at a low voltage.
When a ground voltage is applied to the external input signal VIN 133, the internal input signal VX 134 at the third contact point 132 is switching to a low voltage by the inverter 131. The second transistor 112 is turned on due to the low voltage furnished to its gate terminal connected to the third contact point 132.
Consequently, the external output signal VOUT 114 connected to the drain of the second transistor 112 is grounded through the second transistor 112 and is pulled down to the ground voltage. The external output signal VOUT 114 having a ground voltage is then coupled into the gate of the third transistor 121 and turns on the third transistor 121. The voltage at the second contact point 123 is now pulled up to the high voltage provided by the high supply voltage VCCH through the third transistor 121. The high voltage at the second contact point 123 is then coupled into the gate of the first transistor 111 and turns off the first transistor 111. That is, the external output signal VOUT 114 cannot be pulled up to the high voltage through the first transistor 111.
The gate-source voltage drop of the fourth transistor 122 is about zero voltage because both its gate voltage and its source voltage at the third contact point 132 are held at the same low voltage, which will turn off the fourth transistor 122. The circuit operation process described above forms a self-consistent action.
When a low voltage is applied to the external input signal VIN 133, the internal input signal VX 134 at the third contact point 132 is switching to a ground voltage by the inverter 131. The second transistor 112 is turned off due to the ground voltage furnished to its gate terminal connected to the third contact point 132.
Consequently, the external output signal VOUT 114 connected to the drain of the second transistor 112 cannot be pulled down to the ground voltage. However, the gate-source voltage drop of the fourth transistor 122 is then approximately equal to the low voltage because of the low voltage at its gate terminal and the ground voltage at its source terminal, which means at the third contact point 132, and the fourth transistor 122 is then turned on. The ground voltage at the third contact point 132 is thus coupled to the gate of the first transistor 111 through the fourth transistor 122 and turns on the first transistor 111.
Thereby, the first contact point 113 is electrically connected to the high supply voltage VCCH through the first transistor 111 and the external output signal VOUT 114 can be pulled up to the high voltage. The high voltage at the first contact point 113 is then coupled to the gate of the third transistor 121 and turns off the third transistor 121. Again, the circuit operation process described above forms a self-consistent action.
In the prior art voltage level shifter 100, the fourth transistor 122 of is a thick oxide device, which means that the threshold voltage of the fourth transistor 122 is relatively higher compared with that of a thin oxide device. That is, when the internal input signal VX 134 at the third contact point 132 changes from a ground voltage to a low voltage, the second transistor 112 switches from an off-state to an on-state.
Meanwhile, the fourth transistor 122 switches from an on-state to an off-state. The state switching processes for the second transistor 112 and the fourth transistor 122 must co-act to form a self-consistent operation.
However, a higher threshold voltage of the fourth transistor 122 in conjunction with a fixed low supply voltage VCCL at its gate terminal means that the voltage swing of the internal input signal VX 134 at the third contact point 132 for the fourth transistor 122 to switch on-off state is also larger, which further means a longer time must be taken for state-switching processes. Therefore, a move to a high-speed operation of the internal circuitry may excess the state-switching speed of the related transistors in the voltage level shifter 100, which may cause a malfunction of the voltage level shifter 100.
Please refer to FIG. 2. FIG. 2 is a circuit diagram schematically illustrating another voltage level shifter 200 according to the prior art. The voltage level shifter 200 of the prior art comprises a first transistor 211, a second transistor 212, a third transistor 221, a fourth transistor 222 having a low threshold voltage, and an inverter 231. In addition, there is a reference voltage generator, not shown in the figure, for providing a high supply voltage VCCH and a low supply voltage VCCL.
The inverter 231 comprises a fifth transistor 235 and a sixth transistor 236. The fourth transistor 222 is designed to be a transistor of low threshold voltage or even zero threshold voltage.
The essential operations of the voltage level shifter 200 and the voltage level shifter 100 are the same. However, due to the low threshold voltage of the fourth transistor 222, the voltage swing of the internal input signal VX 234 at the third contact point for the fourth transistor 222 to switch on-off state is smaller, which means the time duration taken for state-switching processes is shorter. Therefore, the voltage level shifter 200 can accommodate itself to a high-speed internal circuitry.
Nevertheless, a leakage pathway may occur to the voltage level shifter 200 in certain situation described below. That is, when a ground voltage is applied to the external input signal VIN 233, the fifth transistor 235 is turned on and the sixth transistor 236 is turned off. The internal input signal VX 234 at the third contact point 232 is then pulled up to a low voltage through the fifth transistor 235 in the inverter 231. The second transistor 212 is turned on due to the low voltage furnished to its gate terminal connected to the third contact point 232.
Ideally, the gate-source voltage drop of the fourth transistor 222 is about zero voltage because both its gate voltage and its source voltage at the third contact point 232 are held at about the same low voltage, which will turn off the fourth transistor 222. However, the voltage of the gate of the fourth transistor 222 is exactly equal to the lower supply voltage VCCL and the voltage at the third contact point 232, which is also the source terminal of the fourth transistor 222, is actually less than the lower supply voltage VCCL due to the inner voltage drop of the inverter 231, which is well known to those skilled in the art.
If the voltage difference between the gate voltage and the source voltage of the fourth transistor 222 excesses the low threshold voltage of the fourth transistor 222, the state of the fourth transistor 222 can not be completely turned off while it should be. Under such circumstance, the on-state third transistor 221 in conjunction with the on-state fourth transistor 222 will result in a power leakage pathway 240 that is shown in FIG. 2 as a dashed line extending from the high supply voltage VCCH to the low supply voltage VCCL through the on-state fifth transistor 235 of the inverter 231. The power leakage pathway 240 will sacrifice the benefit of having lower operating voltage.
Consequently, there is a great need for providing a voltage level shifter capable of high-speed and low-leakage operation.